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74AC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
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HIGH SPEED: fMAX = 300MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74AC74B 74AC74M T&R 74AC74MTR 74AC74TTR
DESCRIPTION The 74AC74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. A signal on the D INPUT is transferred to the Q and Q OUTPUTS during the positive going
transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
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74AC74
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage
4, 10 5, 9 6, 8 7 14
1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC
TRUTH TABLE
INPUTS CLR L H L H H H
X : Don't Care
OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn NO CHANGE CLEAR PRESET
PR H L L H H H
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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74AC74
ABSOLUTE MAXIMUM RATINGS
Symbol V CC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 50 200 -65 to +150 300 Unit V V V mA mA mA mA C C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1) Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 8 Unit V V V C ns/V
1) VIN from 30% to 70% of VCC
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DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 II ICC IOLD IOHD Input Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 VO = 0.1 V or VCC-0.1V VO = 0.1 V or VCC-0.1V IO=-50 A IO=-50 A IO=-50 A IO =-12 mA IO =-24 mA IO =-24 mA IO=50 A IO=50 A IO=50 A IO =12 mA IO =24 mA IO =24 mA VI = VCC or GND VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 2.9 4.4 5.4 2.56 3.86 4.86 0.002 0.001 0.001 0.1 0.1 0.1 0.36 0.36 0.36 0.1 2 TA = 25C Min. 2.1 3.15 3.85 Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 Max. Value -40 to 85C Min. 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1 20 75 -75 0.9 1.35 1.65 2.9 4.4 5.4 2.4 3.7 4.7 0.1 0.1 0.1 0.5 0.5 0.5 1 40 50 -50 A A mA mA V V Max. -55 to 125C Min. 2.1 3.15 3.85 0.9 1.35 1.65 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
V IL
V
VOH
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
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74AC74
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 3.3 5.0
(*)
Value TA = 25C Min. Typ. 7.0 5.0 6.0 4.5 5.0 4.0 4.0 3.0 2.0 2.0 1.0 1.0 100 140 1.5 1.5 -0.2 -0.2 0.2 0.2 -1.0 -0.7 300 300 Max. 14.0 10.0 12.0 9.5 7.0 5.0 4.0 3.0 3.0 3.0 1.0 1.0 90 130 -40 to 85C Min. Max. 16.0 10.5 13.5 10.5 7.0 5.0 4.0 3.0 3.0 3.0 1.0 1.0 90 130 ns -55 to 125C Min. Max. 17.5 12.0 14.0 10.5 ns ns Unit
tPLH tPHL Propagation Delay Time CK to Q or Q tPLH tPHL Propagation Delay Time PR or CLR to Q or Q tW Pulse Width HIGH or LOW, CK or PR or CLR ts Setup Time D to CK HIGH or LOW th tREM fMAX Hold Time D to CK HIGH or LOW Removal Time PR or CLR to CK Maximum Clock Frequency
(**)
3.3 (*) 5.0(**) 3.3 (*) 5.0(**) 3.3 (*) 5.0
(**)
ns
3.3 (*) 5.0
(**)
ns
3.3 (*) 5.0(**) 3.3 (*) 5.0
(**)
ns
MHz
(*) Voltage range is 3.3V 0.3V (**) Voltage range is 5.0V 0.5V
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 5.0 fIN = 10MHz 35 pF TA = 25C Min. Typ. 3 Max. Value -40 to 85C Min. Max. -55 to 125C Min. Max. pF Unit
CIN C PD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per Fli p-Flop)
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74AC74
TEST CIRCUIT
C L = 50pF or equivalent (includes jig and probe capacitance) R L = R1 = 500 or equivalent R T = ZOUT of pulse generator (typically 50)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES, CLOCK PULSE WIDTHS (f=1MHz; 50% duty cycle)
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74AC74
WAVEFORM 2: PROPAGATION DELAYS, RESET AND SET PULSE WIDTHS (f=1MHz; 50% duty cycle)
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74AC74
WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 4: PULSE WIDTH
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74AC74
Plastic DIP-14 MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.100 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.055 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001A
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74AC74
SO-14 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45 (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013G
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74AC74
TSSOP14 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 4.9 6.25 4.3 5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.20 5.1 6.5 4.48 0.002 0.335 0.0075 0.0035 0.193 0.246 0.169 0.197 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.201 0.256 0.176
DIM.
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Swit zerland - United Kingdom (c) http://w ww.st.com
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